CISC vs RISC: The functional and comprehensive differences between CISC and RISC
Today both CISC (Complex Instruction Set Computing) and RISC (Reduced Instruction Set Computing) devices/computers exist in market. There are fundamental differences between these along with their working design.
Though we can’t compare CISC and RISC machines saying this is better and this is NOT, here are some comparisons made between them. Your feedback is sought for this classroom scratches. Also report if there is any ambiguity.
Variable length instruction format found in CISC machine so special decoding package is needed.
- Numbers & Size
A large number of instructions, typically from 100 to 250, are observed in CISC whereas by name reduced are the instructions (60 to 100 approx) in RISC.
For 1 high level instruction, there will be 1 machine level instruction; this is flexible and way of CISC.
Some instructions in CISC perform specialized tasks and are used infrequently as XTHL, SPHL.
RISC: Instructions length is generally fixed and easily decoded.
- c. Stages
CISC instruction stages are comparatively larger than those of RISC ones. This directly affects pipelining performance.
- d. Addressing Modes
A large variety of addressing modes, 5 to 20 different modes are found in CISC. RISC machines see only Register addressing, Immediate addressing and Relative addressing.
The instructions of CISC architecture are of variable length. Instructions that require register operands may be only 2 bytes in length, but instructions that need 2 memory addresses may need 5 bytes in length.
This result in complex decoding logic because packaging of instructions is not uniform. As more instructions and addressing modes are incorporated into a computer, the more hardware logic is needed to implement and support them. And this may cause computation slow.
General Purpose Registers (GPRs):
For CISC: Fewer number of GPRs results in smaller fabrication cost but memory has to be accessed frequently. RISC machines observe relatively large number of registers (around 500 or even more).
Instruction execution generation in CISC needed to access memory frequently which makes it slow. Instructions manipulate operands in memory.
The motive of complex instruction set is desire to simplify the compilation of the program in HLL (High Level Language). The task of compiler is to generate a sequence of machine instruction for each HLL statements.
The task is simplified if there are machine instructions that implement the HLL statements directly. The essential goal of CISC architecture is to attempt to provide a single machine instruction for each statement written in HLL.
Memory access is limited to LOAD and STORE instruction for RISC architecture devices. Memory is not used as operand. All operations are performed with registers in CPU.
Almost all CISC devices are micro programmed so no issues regarding control memory is to be dealt.
This is quite opposite for RISC machines where the control system is hardwired and memory lines are accessed making system faster.
Pipelining and instruction cycle
RISC: Single cycle instruction execution so very fast. Pipelining is entertained.
In fact, though pipelining is the feature of RISC machines, CISC do employ it. Also the pipelining is effective up to certain optimized level in CISC due to comparatively larger instruction stages.
For a quick note:
If there are ‘n’ number of instructions and ‘k’ number of stages in each instruction, the state of each stage is a function of time (let ‘T’ be the time unit). Time requirement for completion of total instruction/operation may be given by following formulae.
Time required without pipelining= nk
Time required with pipelining = k + (n-1)
Finally, speed up due to pipelining implementation for optimized (or large n) = nk / k + (n-1)
This is a theoretically expressions though. It is not sure that increase in number of stages will ameliorate the performance.
Pipelining also allows a trade-off between latency (how long it takes to execute an instruction) and processor bandwidth (how many MIPS the CPU has).
Shared Registers/Register Windows Overlapping (RWO)
Procedure Call and Return occurs quite frequently in HLL. When translated into machine language, a sequence of instructions that share register values, (pass parameters needed for the procedures and then calls a sub-routine to execute the body of the procedure), are generated for each procedure call.
After a procedure return, the program restores the old register values, passes results to the calling program and returns from the sub-routine.
In this whole process of sub-routine call and return- saving and restoring registers, passing of parameters and results, involve time consuming operations. This is a performance bottleneck.
RISC architecture provides multiple register banks and each procedure is allocated its own bank of registers. This eliminates the need for saving and restoring register values.
Each procedure call activates a new register window by incrementing a pointer, while returning decrements the pointer and causes the activation of previous window.
Windows for adjacent procedures have overlapping register that are shared to provide passing of parameters and results.
For a quick note:
Window Size = L + 2C + G
Total number of registers needed in process or register file = (L + C)W + G
Where: L= Local registers, C= Common register to adjacent processes, G= Global registers, W= number of windows
CISC Machines: IBM 370, Intel 80846, Pentium, Motorola 68000, almost all everyday desktop processors
RISC Machines: All research oriented hi-end computers
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